Many serial port arrangements are known in the field of electronic circuits and data communications. For example, arrangements include static serial ports for transmitting and receiving data of a selected serial communications protocol (e.g., Universal Asynchronous Receiver Transmitter (UART) devices), and configurable serial ports (e.g., microprocessors with software controlled serial ports). Configurable serial ports provide the possibility of servicing a multiplicity of protocols with a single serial port device. Static and configurable serial ports are used for a wide range of applications, including communication with display devices, communication with modems, and serving as a universal system connector (USC).
Numerous serial communications protocols (also referred to herein as protocols) have been promulgated (e.g., to name a few, UART, I2C, HC11, IrDa), each defining specific parameters under which serial bits of data are communicated between serial ports. The parameters defining a protocol may include factors such as the timing of bits received or transmitted, electrical parameters (e.g., signal polarity, line driver characteristics, such as open-source or open collector output impedances, etc.), and logical definitions of bit meanings and sequences and sequences.
One example of a configurable serial port is provided by the Motorola M68HC11 family of microcontrollers, which include a programmable serial port known in the art as the Motorola Synchronous Serial Peripheral Interface (SPI). Such serial interfaces may be disadvantageous for several reasons. For example, the processor must execute a software program to control the serial port, and all data bits to be sent over signal paths pass through the processor, thus loading the processor, beyond whatever load is imposed on the processor as the processor performs the tasks for which it is otherwise employed. Also, because the serial hardware is a power-consuming part of the processor, additional power is consumed whenever the processor is executing a software program even if the serial port is inactive.
As an alternative to microcontroller-controlled programmable serial ports, programmable serial ports implementing a finite state machine have been developed to off-load from the processor the burden of having to control many aspects of the serial port. An example of such a programmable serial port is given in U. S. patent application entitled GENERIC SERIAL PORT ARCHITECTURE AND SYSTEM, Ser. No. 09/706,450, by Sorenson, filed Nov. 3, 2000.
FIG. 1 is a block diagram of such a programmable serial port 100. In FIG. 1, when operating in transmit mode, a shift register 110 receives a parallel set of data bits on channels 102 from a buffer 120 and outputs the bits as a serial output on channel 104 (via a driver 180) under the control of a finite state machine (FSM) 120. Conversely, when operating in a receive mode, shift register 110 receives a serial input on channel 104 and outputs a parallel set of data bits on channels 102.
The phrase “finite state machine” is defined herein to be any device that stores an existing status (e.g., a program counter and a plurality of other registers) and upon receiving an input (e.g., an instruction or command), changes to a new status and/or causes a deterministic action or output to take place in response to the existing status and the input. While FSMs may not include an arithmetic logic unit (ALU) or other circuits conventionally associated with microprocessors, the term FSM as defined herein does not exclude devices including such circuitry or elements.
In programmable serial port 100, instructions corresponding to rules for implementing two or more protocols are stored in a memory 130. Using the instructions from memory 130, FSM 120 executes instructions corresponding to a protocol selected by controller 150 to provide an output according to the specified protocol on channel 104. A bit counter 170 provides the FSM 120 with a numbered count of bits transferred, to facilitate providing an output according to the selected protocol, as the processing of a bit frequently depends on the position in either the parallel channels 102 or the received or transmitted serial bit stream on channel 102. Typically an output is directed through a driver 180 to provide an output having (or compatible with) specific electrical parameters. In conventional FSM-based programmable serial ports (e.g., programmable serial port 100), execution of instructions to provide an output according to a selected protocol requires that FSM 120 receive a clock pulse from clock generator 160 and provide a clock signal to shift register 110 to control output of each bit from shift register 110 to channel 104 or buffer 120, as the case may be, and requires that the FSM maintain and process a bit count provided by a bit counter 170.
Providing an output according to a selected protocol requires that an output be provided at specified times. For example, in some protocols, an output on channel 104 must occur within aspecified time period following receipt of a timing signal (e.g., a rising edge on a channel 190) by programmable serial port 100. Because the time interval between receiving the clock signal and providing the output may be very short, an instruction set to achieve an output must be capable of short execution times or the serial port may have inadequate data output speed, and in some instances may be prohibited from serving some output protocols.
FIG. 2 is a flow chart 200 of a typical set of instructions for a conventional programmable serial port to achieve a standard output (e.g., a UART-compatible output). At step 205, the FSM waits for an indication that the shift register is full of data (i.e., a parallel set of data). At step 210, the FSM loads the driver with a start state (e.g., logic value one or zero). At step 220, the FSM initializes the bit counter (e.g. an initial bit count is loaded). At step 240, the FSM identifies the lines of code that define the loop by which data is shifted from the shift register. The first data bit is sent and maintained for as many clock cycles as necessary for the protocol, and the bit counter is decremented by the FSM at steps 250 and 260, respectively. Subsequent data bits are sent and the bit counter is decremented by the FSM (step 270), until the bit counter reaches zero. After all data bits are sent, the FSM causes a parity bit to be sent at step 280. Finally, the driver is set to a stop state at step 290.
One method of achieving faster execution time is to increase the clock rate at which the FSM executes instructions such that a greater number of instructions are executed in a given time interval (e.g., the time interval between a timing signal and commencement of outputting of serial data bits); however, a faster clock rate may require faster and more expensive electronic components. Additionally, a faster clock rate may require an increased power expenditure. Accordingly, a programmable serial port is needed which is able to receive and process any necessary inputs (e.g., timing signals) and provide any necessary outputs at a relatively high speed, while maintaining a relatively low clock speed. Additionally, a programmable serial port is needed which is capable of providing outputs and accepting inputs according to a wide variety of protocols.